Generally, only a single embedded operating system can be operated in a single-core embedded processor system, and during operation of the system, the most crucial system clock interrupt is implemented by converting the time interval of timer interrupt into a specific value, submitting the timer interrupt to the core when the number of a core hardware counter accumulates up to the value of the time interval, and automatically re-loading the counter by the processor; considering that the interval of the timer interrupt should not be too short, the interval of timer interrupt configured in the system is generally set as 10 ms-100 ms, and once a clock interrupt occurs, the system enters a timer interrupt service procedure, ticks (clock tick, which is a relative time unit of the system derived from the periodical interrupt of the timer, one interrupt represents one tick) of the system are accumulated and task scheduling of the operating system is performed.
In a single-core processor, the requirements for synchronization of clock ticks are not high, for example, two software timers are set, the relative interval between timers will not change obviously even if the clock tick interrupt is lost since time deviation is relative to one hardware timer standard, which, therefore, will not have great impact on the service.
Nevertheless, in a multi-core processing system, the number of cores is increasing continuously with the development of technology, two cores, four cores, eight cores, and sixteen cores have become the main trend of various application development. Multi-core and multi-thread technology also develops very fast, a single chip containing 64 or more cores will arise in the coming years, and the expansion of the scale of the system has higher requirements on the clock synchronization. When a multi-core system operates a plurality of embedded operating systems, for example, each core separately operates embedded operating systems such as vxWorks and Linux, as shown in FIG. 1, each core 10 in a multi-core system 20 separately implements the function of system clock counting through the clock interrupt 30. Due to reasons like unbalance of operation load of each core, the system clock tick of the embedded operating system operated on each core cannot keep synchronous with each other, on the contrary, the system clock ticks of different cores will have a large deviation with the increase of operating time of the system. Since an upper-layer software timer is generally set based on the system clock tick, such a deviation, if up to a certain point, will have a strong impact on the accuracy and synchronization of upper-layer application software timers between different cores. For example, it is assumed that the tick of each clock interrupt in the operating system is 10 ms, if a timer with a duration of 10000 ticks is set in an operating system of a plurality of cores, load unbalance of a certain core will also cause loss of the clock interrupt of the core, thus causing ticks to have a deviation. When the accumulated deviation between clock ticks of different cores reaches 5 ticks, namely 50 ms, this will not be tolerable in some applications sensitive to time.